Method for improving the data transfer in semi synchronous clock domains integrated circuits at any possible m/n clock ratio
Abstract
A method for data transfer between two semi-synchronous clock domains in a System on Chip (SoC) includes first and second integrated processors or circuits respectively operating at first and second clock frequencies The SoC includes a phase for detecting, for each frequency ratio between the first and second clock frequencies, a maximum rate of the data transfer, with the rate being a function of all the possible input and output delays supported by the SoC. This is dependent on the parameters of the SoC. There is also a phase for programming a generic frequency converter between the first and second integrated processors for the data transfer, and a phase for scheduling the data transfer between the semi-synchronous clock domains.
Classe Tecnologica
G - Physics
Patent Office
United States Patent and Trademark Office
Numero Deposito
US7676685
Anno Deposito
2006
Anno Concessione
2010
Inventori Pugliesi
- Giotta Francesco
Tutti gli inventori
- Marco Castano
- Salvatore Pisasale
- Carmine Ciofi
- Francesco Giotta
Titolari pugliesi
- Non ci sono titolari pugliesi
Tutti i titolari
- STMicroeletronics S.r.l.
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