Abstract

In this paper an integrated circuit (IC) design of the fractional order proportional-integral-derivative (PID) controller is proposed. The development of the IC device is realized in Cadence environment, using the switched capacitors (SC) technology in order to reduce the area on the silicon wafer and to improve the electrical controllability. In order to obtain transfer functions that describe the fractional order of the differ-integral operator it is necessary to use interpolation methods, in particular, the choice in this work has fallen on the Oustaloup interpolation. This procedure is aimed at implementing a series of pole-zero blocks that approximate the non-integer order. The realized approach is able to guarantee a good approximation of the fractional order PID and simultaneously propose a detailed circuit analysis of the influence of the non-idealities, in particular the phenomenon of warping. This takes into account the distortion introduced by the s-domain to the z-domain transition, acting on the positions of poles and zeros, especially those at a higher frequency. Time and frequency domain result tests confirm the feasibility and reliability of the SC implementation.

Autore Pugliese

• Maione Guido

Tutti gli autori

• Caponetto R , Dongola G , Maione G , Pisano A

Titolo volume/Rivista

JOURNAL OF VIBRATION AND CONTROL

Anno di pubblicazione

2014

ISSN

1077-5463

ISBN

Non Disponibile

Numero di citazioni Wos

Nessuna citazione

Ultimo Aggiornamento Citazioni

Non Disponibile

Numero di citazioni Scopus

4

Ultimo Aggiornamento Citazioni

2017-04-22 03:20:59

Settori ERC

Non Disponibile

Codici ASJC

Non Disponibile