Abstract

Power consumption of high-speed low-resolution analog-to-digital converters (ADCs) can be reduced by means of calibration. However, this solution has some drawbacks such as time slot allocation for calibration and die area increase. This paper presents a 5-bit 1-Gs/s ADC without calibration, fabricated in 90-nm CMOS. Low power consumption has been ensured by operating at both architecture and comparator levels. A folded interpolated architecture has been adopted. However, compared to standard solutions that use static preamplifiers, the interpolation technique has been implemented by taking recourse to dynamic comparators, enabling significant power saving. Moreover, despite the high operating frequency, intrinsic matching has been ensured while keeping low power consump- tion. The ADC uses double-tail dynamic comparators, operating with a fixed bias current and with reduced kickback noise. Large input transistors are used to guarantee the targeted matching, thereby avoiding calibration. The ADC achieves 4.3b-ENOB (effective number of bits) and 260-MHz effective resolution bandwidth while consuming 7.65 mW from a 1.2 V supply. The ADC figure of meritis 0.39 pJ/conv. step, which is the state-of- the-art performance for an uncalibrated ADC at this sampling frequency and resolution.

Autore Pugliese

• D'amico Stefano

Tutti gli autori

• S. D'Amico , G. Cocciolo , A. Spagnolo , M. De Matteis , A. Baschirotto

Titolo volume/Rivista

IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT

Anno di pubblicazione

2014

ISSN

0018-9456

ISBN

Non Disponibile

Numero di citazioni Wos

8

Ultimo Aggiornamento Citazioni

28/04/2018

Numero di citazioni Scopus

14

Ultimo Aggiornamento Citazioni

28/04/2018

Settori ERC

Non Disponibile

Codici ASJC

Non Disponibile