RECONFIGURABLE TURBO INTERLEAVERS FOR MULTIPLE STANDARDS

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Abstract

A data processing system, a turbo decoding system, an address generator and a method of reconfiguring a turbo decoding method is provided. The data processing system (101) comprises the turbo decoding system (100). The turbo decoding system (100) comprises electronic circuits. The electronic circuits comprises: a memory (108), the address generator (102), and a Soft Input Soft Output decoder (106). The address generator (102) is operative to produce a sequence of addresses according to an interleaving scheme. The address generator can support multiple interleaving schemes. The address generator (102) is operative to receive reconfiguration information. The address generator (102) is operative to reconfigure during operational use the interleaving scheme in dependency on the reconfiguration information.

Classe Tecnologica

G - Physics

Patent Office

United States Patent and Trademark Office

Numero Deposito

US2011087949

Anno Deposito

2009

Anno Concessione

2011

Inventori Pugliesi

  • Dilonardo Angelo Raffaele

Tutti gli inventori

  • Angelo Raffaele Dilonardo
  • Nur Engin

Titolari pugliesi

  • Non ci sono titolari pugliesi

Tutti i titolari

  • NXP B.V.