Method for low-stress multilevel reading of phase change memory cells and multilevel phase change memory

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Abstract

According to a method for multilevel reading of a phase change memory cell a bit line (9) and a PCM cell (2) are first selected and a first bias voltage (VBL, V00) is applied to the selected bit line (9). A first read current (IRD00), that flows through the selected bit line (9) in response to the first bias voltage (VBL, V00), is compared with a first reference current (I00). The first reference current (I00) is such that the first read current (IRD00) is lower than the first reference current (I00), when the selected PCM cell (2) is in a reset state, and is otherwise greater. It is then determined whether the selected PCM cell (2) is in the reset state, based on comparing the first read current (IRD00) with the first reference current (I00).; A second bias voltage (VBL, V01), greater than the first bias voltage (VBL, V00), is applied to the selected bit line (9) if the selected PCM cell (2) is not in the reset state.

Classe Tecnologica

G - Physics

Patent Office

United States Patent and Trademark Office

Numero Deposito

US7885101

Anno Deposito

2008

Anno Concessione

2010

Inventori Pugliesi

  • Ferraro Marco

Tutti gli inventori

  • Ferdinando Bedeschi
  • Claudio Resta
  • Marco Ferraro

Titolari pugliesi

  • Non ci sono titolari pugliesi

Tutti i titolari

  • Numonyx B.V.